On Wed, 23 Jul 2008 17:17:59 +0200, "Norman Bollmann"

What sort of speeds are you dealing with? Under 100MHz with rise times
that aren't too fast shouldn't require anything special. We're running
64MB DDR2 at 200MHz clock rates with no terminations. It's amazing how
beautiful the signals look.

The trick to our madness is using only one memory chip per bus
connection and keeping the connections short. On our board, the
longest trace between the FPGA and the memory is 0.800". Our flash
memory is less stringent, so some of the traces are 1.5". Any of the
edge sensitive lines are kept as short as practical. You may consider
putting terminations on the clock lines if the trace lengths get too
long.

This technique will fall apart if you gang multiple memory devices.
The key here is no stub connections in the middle of the trace and
short runs.

All of our traces were sandwiched between power and ground planes
mainly to reduce EMI. Something that is really helpful is being able
to control the rise/fall times of your signals. On an FPGA, no
problem. Unfortunately, I don't think your processor has variable
drive control.

As to trace impedance, around 50 to 100 ohms is want you want to aim
for. You're kind of forced into the 50 to 100 ohm region by virtue of
the practical aspects of the PCB layout. We're getting about 50 ohms
on or our boards using 5 mil trace width buried between two planes
with 8 mil separation between the layers for single ended traces and
around 100 ohms for the differential clock signals. On some of our
boards, we design 100 ohm differential traces for signals running on
LVDS. With LVDS, you're stuck designing to 100 ohms if you want to
stay within bounds of the spec.

--
Mark